1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor (FET) having a gate electrode, such as a GaN-based FET having a gate electrode for use in a power amplifier.
2. Description of the Background Art
In an FET for use in a power amplifier required to have a high breakdown voltage, a field plate is often provided in its gate electrode to relax electric field concentration in the drain electrode side end portion of the gate electrode, thereby reducing Schottky reverse leakage and improving a drain breakdown voltage.
FIG. 2 shows a conventional FET having a field plate disclosed in U.S. patent application publication No. 2006/0102929 A1 to Okamoto et al. This FET has a cross-sectional structure shown in FIG. 2, including an undoped GaN semiconductor layer having a buffer layer 11, a channel layer 12, and an electron supply/Schottky barrier layer 13 formed on a substrate 10 in this order, a source electrode 1, a gate electrode 2, and a drain electrode 3 being arranged on the top surface of the GaN semiconductor layer. An insulating film 21 isolates the source electrode 1 from the gate electrode 2, and the gate electrode 2 from the drain electrode 3. A field plate 5 is provided which overhangs the insulating film 21 from the gate electrode 2 toward the side of the drain electrode 3 in a visored shape.
This FET is manufactured by the following steps as FIGS. 3-7 showing the manufacturing method. In the first step, FIG. 3, the buffer layer 11, the channel layer 12, and the electron supply/Schottky barrier layer 13 are formed on the surface of the substrate 10 made of sapphire, SiC, Si, or the like in this order. The buffer layer 11 is designed in configuration depending upon the material of the substrate 10. For example, in the case of an SiC substrate, the buffer layer 11 is constituted by an AlN film having its film thickness of about 0.1 μm and a GaN film having its film thickness of about 0.5 μm. The channel layer 12 is a GaN film having its film thickness of about 2 μm and serving as an electron transport layer. The electron supply/Schottky barrier layer 13 is an AlGaN film having its film thickness of about 20 nm and including about 20 percent of Al.
Next, on the electron supply/Schottky barrier layer 13, metal such as Ti/Al is evaporated to form the source electrode 1 and the drain electrode 3, and then these electrodes are annealed at 650 degree centigrade to provide ohmic contact between these electrodes and the layer 13.
In the second step 2, FIG. 4, on the surface of the electron supply/Schottky barrier layer 13 between the source electrode 1 and the drain electrode 3, the insulating film 21 made of SiN is formed by a plasma-enhanced CVD (Chemical Vapor Deposition) method or the like.
In the third step 3, FIG. 5, a part of the insulating film 21 is removed by etching to provide an opening HA for forming the gate electrode 2 so that the electron supply/Schottky barrier layer 13 is exposed.
In the step 4, FIG. 6, on the top of these layers provided with the source electrode 1, the drain electrode 3 and the opening HA, a resist material is applied to form a photoresist pattern 30 having an opening HB exposing an area for forming the gate electrode 2 and a field plate 5 by a photolithography technique. Further, a residue of the resist material is removed by an O2 plasma ashing.
Finally, in the fifth step 5, FIG. 7, Ni/Au is evaporated through the opening HB of the photoresist pattern 30 to form the gate electrode 2 and the field plate 5 into one. This forms the gate electrode 2 joined with the electron supply/Schottky barrier layer 13 by Schottky junction, and the field plate 5 overhanging the insulating film 21 from the gate electrode 2 to the drain electrode 3 side in a visored shape. Thereafter, the photoresist pattern 30 and Ni/Au deposited thereon are removed to thereby obtain the structure in FIG. 2.
Since the Group III nitride semiconductor including GaN is used for this FET, the FET has a wide band gap, a high dielectric breakdown electric field, and high electron saturation drift velocity. Further, because carrier gas can be utilized bi-dimensionally by the heterojunction, the FET is expected as an electronic device which is excellent in high-temperature operation, high-speed switching operation, large-power operation, and the like.
However, the above-described FET has the following problems. The first problem is that the field plate 5 tends to be separated from the insulating film 21. Metal Ni/Au is used for forming the field plate 5 and the gate electrode 2 into unity. Thereby, the problem is caused by a low adhesiveness between the Ni and SiN used for the insulating film 21. As a result, the problem can be caused by the field plate 5 likely to be separated from the insulating film 21 by a small disturbance.
Ti/Pt/Au is normally used for the gate electrode in a conventional GaAs-based FET. Since the adhesiveness between Ti and SiN is superior, such a problem is not caused which involves the separation. Also, since joining Ti with GaN is ohmic contact as employed with the source electrode 1 and the drain electrode 3, it cannot be used for the gate electrode requiring Schottky junction.
The second problem is that, in the fourth step, the O2 plasma ashing is performed to remove the residue of the resist material when the photoresist pattern 30 is formed which has the opening HB exposing the area for forming the gate electrode 2 and the field plate 5. This O2 plasma ashing oxidizes the surface of the electron supply/Schottky barrier layer 13 in the area for forming the gate electrode 2 thereafter to form an oxidized film between the gate electrode 2 and the electron supply/Schottky barrier layer 13. Thereby, a problem that a gate leakage current increases is caused, as described in Tamotsu HASHIZUME, et al., “Surface Control Process of AlGaN for Suppression of Gate Leakage Currents in AlGaN/GaN Heterostructure Field Effect Transistors” Japanese Journal of Applied Physics, Vol. 45, No. 4, pp. L111-L113.